Memory controller and a cache for accessing a main memory, and a system and a method for controlling the main memory

ABSTRACT

A memory control system has a replacement detection/notification circuit for detecting occurrence of replacement of dirty entry in a cache and informing a memory controller of the detection, and a state control circuit for precharging the currently active page in a main memory when the memory controller is informed of the detection and a preceding access to the main memory attendant upon the replacement of dirty entry is completed. By precharging the active page in the main memory to return to the idle state when the preceding access attendant upon the replacement of dirty entry is completed, the succeeding access can be done only by activating the aimed page probably different from the above page. It is thereby obviated to return the activated page due to the preceding access to the idle state after a page miss occurs in the succeeding access.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a memory controller, a cachedevice, a memory control system, a memory control method, and arecording medium, particularly to a technique for controlling a storagedevice in which data I/O is made fast.

[0003] 2. Description of the Related Art

[0004] In recent years, as the clock speeds of CPUs in computer systemsbecome higher or the processing speeds of various other electroniccircuits become higher, high-speed interfaces are required. For thispurpose, by exploiting the fact that addresses of a storage devicesuccessively output from a CPU are mostly near to each other, DRAMs(Dynamic Random Access Memories) after a high-speed DRAM use a functionof keeping an area, which has been activated in a memory cell array,active for a while to achieve the faster subsequent access to the area.

[0005]FIG. 1 shows a schematic arrangement of a DRAM. Referring to FIG.1, a memory cell array 35 comprises a plurality of word lines, aplurality of bit lines perpendicular to the word lines, and a pluralityof memory cells located at the intersections of the word and bit lines.Upper bits of an address externally input to an address buffer 31indicate a row address, and lower bits thereof indicate a columnaddress. The row address is held in a row address buffer 32, and thecolumn address is held in a column address buffer 33.

[0006] The row address held in the row address buffer 32 is decoded by arow decoder 34 to select one word line in the memory cell array 35. In areadout operation, data in the respective memory cells connected to theselected word line are read out onto the corresponding bit lines assmall voltages, which are amplified by a sense amplifier 36.

[0007] The column address held in the column address buffer 33 isdecoded by a column decoder 37 to open the column gate for one bit linecorresponding to the decoded column address. Data on the thus selectedbit line is output onto a common line 40 through the opened column gate.In a readout operation, the thus obtained data DQ is externally outputthrough a data I/O buffer 38.

[0008] In a writing operation, data DQ externally input through the dataI/O buffer 38 is supplied to a bit line in the memory cell array 35through the common line 40 and the corresponding column gate selectedaccording to a given column address. The data is written in a memorycell on the intersection of the bit line and a word line selectedaccording to a given row address.

[0009] The above-mentioned elements 31 to 38 are under control of acontrol circuit 39. The control circuit 39 is externally supplied with arow address strobe signal/RAS, a column address strobe signal/CAS, and awrite enable signal/WE. Note that an inverted signal expressed by asignal name with an overline in FIG. 1 (and FIGS. 7 to 10) will beexpressed by attaching symbol “/” to the signal name in thespecification.

[0010] In this type of DRAM, successive accesses for readout and writing(read/write) are mostly done to addresses near to each other. Aftercompletion of an access to a row address, the same row address is morelikely to be accessed next. For this reason, when there arises nonecessity to make an access to a different row address, a word lineselected according to a row address is kept active so that thesubsequent accesses can be made by selecting a column address only. Afaster access is thereby attained.

[0011] In order to use such a function more effectively, a recent memorycontroller controls a block of a predetermined size (one word line) tobe kept active even after data in the block was accessed according to agiven address, so as to be able to respond faster when the same block issuccessively accessed. The unit size for such a block is called “page”,and there is a case that a DRAM utilizing this function is called “fastpage DRAM”.

[0012] On the other hand, it is a common practice for recent computersystems to insert a cache memory, which is composed of memory elementsfaster than those of a main memory, between a CPU and the main memoryfor the reason that data once accessed is more likely to be accessedagain in the near future. More specifically, once accessed data in themain memory is registered in the cache memory, and, when the same datais accessed next, it is read out from not the main memory but the cachememory. The access speed to the main memory is thereby apparentlyincreased.

[0013] In this computer system with the cache memory, when an accessrequest to data in the main memory is issued, the cache memory is firstreferred to. If the requested data is present in the cache memory (cachehit), the data is immediately transferred to a CPU. If the requesteddata is not present in the cache memory (cache miss), a block of anappropriate size including the requested data is read out from the mainmemory, and stored in the cache memory. At this time, if no empty blockis available in the cache memory, a block that is least likely to beused again is selected and replaced by the new data.

[0014] Cache memories are roughly classified into store-through type andstore-back type. In the store-through type, when the cache contents arerewritten, the main memory contents are always rewritten accordingly, sothat the latest data are surely stored also in the main memory.Contrastingly in the store-back type, only the cache contents arerewritten, and, when a block is to be re-assigned due to a cache miss,the latest contents of the cache memory is written back to the mainmemory. In case of the store-back type, there is therefore a case thatthe contents of the cache memory differ from those of the correspondingpart of the main memory.

[0015] In the store-back type, the area in the cache memory where onlycache contents have been rewritten is called “dirty entry”. When blocksare re-assigned, as to a block including no dirty entry, thecorresponding block can be simply loaded from the main memory. As to ablock including a dirty entry, however, its contents must be written outto the corresponding block in the main memory, and then another block inthe main memory is assigned to the block in the cache memory. Such anoperation is called “replacement of dirty entry”.

[0016] In recent years, as CPUs become faster and cache capacitiesbecome larger, the store-through type that must frequently access a mainmemory is being replaced by the store-back type that must lessfrequently access the main memory. This is because the access speed to amemory is often considered an important factor of the performance of adata processing system.

[0017]FIG. 2 shows a schematic arrangement of a cache memory. As shownin FIG. 2, the cache memory generally comprises a cache (data area) 41for storing some data stored in a main memory, and a tag memory (tagarea) 42 for storing a part of the address (tag) on the main memorycorresponding to each of the data stored (as entries) in the cache 41.

[0018] Since the cache 41 has a smaller capacity than the main memory,the addresses corresponding to respective entries in the cache 41 areregistered in the tag memory 42. The address of data requested by anaccess request from a CPU is compared with each of the registeredaddresses in the tag memory 42. A cache hit or miss is determined byjudging whether or not the address of the requested data coincides withone of registered addresses in the tag memory 42, i.e., whether therequested data is present in the cache 41 or not.

[0019] In this case, however, huge-size hardware is required if theaddress of the requested data is straightly compared with all of theentries in the cache 41, i.e., all of the tags in the tag memory 42. Forthis reason, the following scheme (set associative memory scheme) isused in general. Entries having lower bits equal to those (INDEX) of theaddress attendant upon the access request are selected from among allentries in the cache 41, and then the address is compared with the tagsof only the selected entries in a comparator 43. Using the lower bits ofthe address attendant upon the access request is because of intensivelocalization of successive access requests from the CPU. Successiveaccesses are apt to concentrate in a narrow range of addresses.

[0020] The same applies to memory control of such a fast page DRAM asdescribed above. More specifically, a row address of the DRAM isassigned to an upper address portion, and a column address is assignedto a lower address portion, so that successive access requests have anidentical row address (page hit) with high probability. When a page hitoccurs, the subsequent access is controlled only with output a columnaddress while the hit page is kept active (page access scheme). Theaccess speed increases because no row address need be output.

[0021] When a recently prevalent store-back cache memory is connected toa memory controller for a conventional fast page DRAM, however, thefollowing problem arises. When a main memory is accessed for performinga replacement of dirty entry in the store-back cache memory, successiveaccess requests having an identical lower address but different upperaddresses are made with high probability, and, in most cases, pagemisses occur in the main memory.

[0022] When either of the successive access requests result in a pagehit, faster accesses can be assured. But, when a page miss arises insuccessive access requests due to an difference in row address, overheadarises in the subsequent access, in which the page having been selectedaccording to the preceding access is precharged to return from theactive state to the non-activated state (called idle state) before theaimed page is activated.

[0023] In a memory controller for a synchronous DRAM (SDRAM: SynchronousDynamic Random Access Memory), the overhead ratio is especially highbecause of a high-speed interface. When a benchmark test was performedin which the run time of a standard program with frequent accesses todifferent memory areas was measured using such an SDRAM memorycontroller and a store-back cache memory, nearly 20% overhead wasobserved. When overhead arises, the access speed lowers accordingly.

[0024]FIG. 3 is a flow chart showing the flow of page control in aconventional memory controller. Referring to FIG. 3, after a DRAM isreset (step S1), it is in the idle state in which none of word lines isselected (step S2). If an access request is given by a CPU (step S3),one word line (page) is selected according to a row address attendantupon the access request, and activated (step S4). One bit line is thenselected according to a column address attendant upon the accessrequest, and a read/write operation is performed. After that, theselected page is kept active.

[0025] If no access request is given by the CPU in the step S3, it ischecked whether the DRAM is to be refreshed or not (step S8). If NO inthe step S8, the flow returns to the step S2 to wait for an accessrequest. Otherwise, the DRAM is refreshed (step S11).

[0026] Also in case that no access request is given by the CPU while apage is active (step S5), it is checked whether the DRAM is to berefreshed or not (step S9). If NO in the step S9, the flow returns tothe step S4 to wait for an access request. If it is judged in the stepS9 that the DRAM is to be refreshed, the currently selected page isprecharged (step S10), and then the DRAM is refreshed (step S11).

[0027] If an access request is given by the CPU in the step S5, a pagehit or miss is judged by checking whether or not the row addressattendant upon the access request is the same as the row address giventhe last time (step S6). In case of page hit, the flow returns to thestep S4 to keep the page corresponding to the row address active, and aread/write operation is immediately performed according to the columnaddress attendant upon the access request.

[0028] In case of page miss in the step S6, the currently selected pageis precharged (step S7) to return from the active state to the idlestate (step S2). After that, the flow advances to the step S4 via thestep S3 to activate another page. That is, in case of page miss,overhead arises that the currently selected page must be returned fromthe active state to the idle state before another page is activated.

SUMMARY OF THE INVENTION

[0029] It is an object of the present invention to attain a more fasteraccess speed to a memory having a fast page function that the pageactivated according to an access is kept in the active state after thatso as to make the subsequent access to the same page faster, byobviating the necessity of resetting the page from the activated stateto the idle state when a page miss occurs.

[0030] A memory controller according to the present invention is forcontrolling access to a main memory. The controller has a mode forkeeping the accessed page in the main memory active even after theaccess is completed, and comprises state control circuit for controllingto precharge the accessed page in the main memory to return to the idlestate upon completion of preceding access on condition that access tothe main memory is attendant upon a replacement of dirty entry in acache device.

[0031] A store-back cache device according to the present inventioncomprises detection/notification circuit for detecting occurrence ofreplacement of dirty entry, and sending a signal to a controller of amain memory. The signal indicates whether or not the current access tothe main memory is attendant upon the replacement of dirty entry.

[0032] A memory control system according to the present inventionsubstantially comprises the above memory controller and the above cachedevice.

[0033] When an access to the main memory is done for a replacement ofdirty entry in the cache device, the succeeding access to the mainmemory highly probably results in a page miss. According to the presentinvention, however, since the active page in the main memory isprecharged to return to the idle state upon completion of precedingaccess before the succeeding access attendant upon the replacement ofdirty entry is completed, the succeeding access can be done only byactivating the aimed page in the idle state. It is thereby obviated toreturn the activated page due to the preceding access to the idle stateafter a page miss occurs in the succeeding access.

[0034] A memory controller according to another aspect of the presentinvention is for controlling access to a plurality of main memories. Thecontroller has a mode for keeping the accessed page in one of the mainmemories active even after the corresponding access is completed, andcomprises state control circuit for controlling to precharge theaccessed page in one of the main memories to return to the idle stateupon completion of preceding access on condition that successiveaccesses attendant upon a replacement of dirty entry in a cache deviceare made to the same one of said main memories.

[0035] A store-back cache device according to another aspect of thepresent invention comprises detection/notification circuit for detectingoccurrence of replacement of dirty entry in a cache and a condition thatsuccessive accesses attendant upon the replacement are made to the sameone of a plurality of main memories, to send a signal to a controller ofthe main memories. The signal indicates whether or not the currentaccess to the one of the main memories is attendant upon the replacementof dirty entry.

[0036] A memory control system according to another aspect of thepresent invention substantially comprises the above second memorycontroller and the above second cache device.

[0037] According to the second aspect of the present invention, evenwhen a dirty entry is replaced, if successive accesses attendant uponthe replacement of dirty entry are made to different main memories,respectively, control is made not to precharge the active page in theearlier accessed main memory.

[0038] Even in accessing for a replacement of dirty entry in the cachedevice, if different main memories are to be successively accessed, apage miss hardly occurs at that time. So, according to the presentinvention, when different main memories are successively accessed,precharging is not performed. Unnecessarily precharging can be avoidedthereby.

[0039] According to still another aspect of the present invention, whena signal indicating whether the present access is attendant upon areplacement of dirty entry or not is sent from the cache device to thememory controller, the signal is included in a signal for indicating atype of access to the main memory.

[0040] According to this aspect of the present invention, the signal canbe sent using an existing signal line without providing any dedicatedsignal line.

BRIEF DESCRIPTION OF THE DRAWINGS

[0041]FIG. 1 is a schematic block diagram showing the arrangement of aDRAM;

[0042]FIG. 2 is a schematic block diagram showing the arrangement of acache memory;

[0043]FIG. 3 is a flow chart showing the flow of page control by aconventional memory controller;

[0044]FIG. 4 is a schematic block diagram showing an example of thearrangement of a computer system which comprises a memory controller anda cache device according to the present invention;

[0045]FIG. 5 is an imaginary view for illustrating the operation of areplacement of dirty entry;

[0046]FIG. 6 is a flow chart showing the flow of page control by thememory controller according to the first embodiment of the presentinvention;

[0047]FIG. 7 is a timing chart showing an example of the operationwaveforms in case of a page hit in an SDRAM memory controller;

[0048]FIG. 8 is a timing chart showing an example of the operationwaveforms in case of a page miss in a conventional SDRAM memorycontroller;

[0049]FIG. 9 is a timing chart showing an example of the operationwaveforms in case of a page miss in an SDRAM memory controller accordingto the first embodiment of the present invention;

[0050]FIG. 10 is a schematic block diagram showing the arrangement of anSDRAM used in the second embodiment of the present invention;

[0051]FIGS. 11A and 11B are imaginary views for illustrating addressassignment used in the second embodiment; and

[0052]FIG. 12 is a schematic block diagram showing another example of acomputer system which comprises a memory controller and a cache deviceaccording to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0053] Embodiments of the present invention will be describedhereinafter with reference to the accompanying drawings.

[0054]FIG. 4 is a schematic block diagram showing the arrangement of amemory control system (computer system) that comprises a memorycontroller and a cache device according to the first embodiment of thepresent invention. Referring to FIG. 4, a CPU 1 is a central processingunit for executing various commands on the basis of a control programsupplied from a ROM 5, RAM 4, or the like via an access control line 6,an address line 7, and a data line 8 of a bus.

[0055] The CPU 1 outputs an access request to a main memory 4, a typesignal indicating the types (type of read/write, type of access to aunit of data or access to a data block, etc.) of the access request, andan address signal, and inputs or outputs data in accordance with thosesignals. The access request to the main memory 4 is issued via a cachememory 2. This is because the access response speed of the main memory 4with a large capacity is relatively low, and so a copy of data is storedin the high-speed cache memory 2 to attain a faster access response.

[0056] The main memory 4 is a storage device such as an SDRAM with afast page mode having the arrangement shown in FIG. 1 for example. Thecache memory 2 is a temporary storage device (buffer storage device)having a smaller capacity than the main memory 4, and composed of memoryelements of higher speed than those of the main memory 4.

[0057] In recent years, as the cache capacity increases, the store-backtype of cache memory is used also in the field of microcontrollers inplace of the store-through type. Also in this embodiment, a store-backmemory is used as the cache memory 2. The cache memory 2 of thisembodiment has the arrangement shown in FIG. 2, and uses a setassociative memory scheme in which entries are selected with lower bitsof a given address, and the given address is compared with only theaddresses corresponding to the selected entries.

[0058] A memory controller 3 is a block for converting an access requestfrom the cache memory 2 into an access protocol for the main memory 4.This memory controller 3 outputs access control signals such as a rowaddress strobe signal/RAS, a column address strobe signal/CAS, and awrite enable signal/WE (see FIGS. 7 to 9) to the main memory 4. Thereason why the memory controller 3 is constructed as a separate blockfrom the cache memory 2 is that various types of memories can beselectively used as the main memory 4 by changing the type of memorycontroller 3.

[0059] In this arrangement, when the CPU 1 issues an access request todata in the main memory 4, it is first checked whether a copy of thedata is present in the cache memory 2 or not. When the copy is present(cache hit), the access can be completed only by communicating with thecache memory 2. In many cases, the CPU 1 will repetitively generateaccess requests to the once accessed data (command) in the near future.In that case, the cache hit probability becomes high, and faster accessfor data I/O can be attained.

[0060] When there is no copy of the data corresponding to the accessrequest in the cache memory 2 (cache miss), the cache memory 2 sends theaccess request to the memory controller 3. The memory controller 3thereby actually accesses the main memory 4 to read out the requesteddata. At this time, a block of an appropriate size including therequested data is read out from the main memory 4, and registered in anentry of the cache memory 2.

[0061] In the cache memory 2 that uses the store-back scheme and setassociative memory scheme, when a dirty entry is to be replaced due to acache miss, the contents of the dirty entry in the cache memory 2 mustbe written out into the main memory 4. As a result, read and writeaccesses with a set of addresses (called set address) are successivelymade.

[0062] More specifically, the dirty entry must be replaced in theprocess of (1) to (3) shown in FIG. 5 by the corresponding numberscircled. Data of a predetermined block including a dirty entry is readout from the cache memory 2, and saved temporarily in a buffer 9 ((1)).The data corresponding to the access request given at that time is thenread out from the main memory 4, and a block including the data isregistered in the area in the cache memory 2 where the dirty entry waspresent ((2)). After that, the contents of the dirty entry temporarilysaved in the buffer 9 are written in the main memory 4 ((3)).

[0063] In the set associative memory scheme, as shown in FIG. 2, entriesare selected by using a lower address attendant upon the given accessrequest as a key, and an upper address attendant upon the access requestis compared with those of the addresses corresponding to the selectedentries to judge a cache hit or miss. Hence, when a replacement of dirtyentry is performed due to a cache miss, successive addresses given foraccessing the main memory 4 for the replacement highly probably haveidentical lower bits but different upper bits.

[0064] That is, when a replacement of dirty entry is performed, read andwrite accesses with a set of addresses having an identical lower addressbut different upper addresses are successively generated. Such anidentical lower address but different upper addresses cause a page missin the main memory 4 due to the difference in row address between twosuccessive accesses.

[0065] In short, when a cache miss has occurred in the cache memory 2 inresponse to a given access request from the CPU 1 and a dirty entry inthe cache is replaced, a page miss occurs with very high probability inthe main memory 4 in subsequent accesses attendant upon the replacement.

[0066] In this embodiment, as shown in FIG. 4, the store-back cachememory 2 is provided with a replacement detection/notification circuit11, which detects a replacement of dirty entry, and gives the memorycontroller 3 a page control signal indicating whether the current accessis attendant upon the replacement or not. The replacementdetection/notification circuit 11 outputs an internal state signalindicating whether a replacement of dirty entry is performed or not, tothe memory controller 3 outside the cache memory 2 as a page controlsignal in synchronism with the corresponding access.

[0067] The memory controller 3 comprises a state control circuit 12 tomake control for setting the respective memory cells in the main memory4 active or idle. When the state control circuit 12 receives from thereplacement detection/notification circuit 11 a page control signalindicating that the current access is attendant upon a replacement, thestate control circuit 12 makes control for returning the currentlyactive page in the main memory 4 to the idle state by prechargingimmediately when the preceding access attendant upon the replacement iscompleted.

[0068] Since the main memory 4 is accessed only after a cache missoccurs, a replacement of dirty entry due to a cache miss can be detectedprior to a page miss that may occur at the time of accessing the mainmemory 4. So, in successive accesses attendant upon a replacement ofdirty entry, when the preceding access is completed, the currentlyactive page in the main memory 4 is immediately precharged so that thesucceeding access can be made only by activating the aimed page in theidle state.

[0069] According to this embodiment, when a page miss occurs in the mainmemory 4, it is possible to avoid overhead that the currently activepage is precharged to return to the idle state before activating anotherpage. For example, as a result of a benchmark test like that for theprior art, overhead can be suppressed to about 10%.

[0070]FIG. 6 shows the control flow of the memory controller 3 in thiscase. The difference from the control flow of the conventional memorycontroller shown in FIG. 3 is that the process of a step S20 is insertedbetween the steps S3 and S4 to check whether or not a page controlsignal, i.e., a dirty entry replacement detection signal is suppliedfrom the replacement detection/notification circuit 11 in the cachememory 2, and to make the flow jump to the step S7 to precharge when thesignal is supplied.

[0071] In this embodiment, when an access to the main memory 4 iscompleted, the accessed page is not unconditionally kept in the activestate but it can be selected whether the page is kept in the activestate or precharged to return to the idle state, in accordance with apage control signal from the cache memory 2. When a page miss occurs,the prior art has need of three processes, i.e., inactivation of thelately accessed page by precharging, activation of another page byoutputting a row address, and output of a column address. In thisembodiment, the necessity of precharging the lately accessed page can beobviated because precharging it had been done before the page missoccurs in practice.

[0072] Note that the memory controller 3 may be controlled as follows.When an access to the main memory 4 is made due to a cache miss, theaccessed page at that time is unconditionally precharged after theaccess is completed. In this method, however, the fast page mode of themain memory 4 cannot be used effectively. That is, in the method ofunconditionally precharging the accessed page after completion of theaccess, the process of page activation must always be done even in caseof an access other than that attendant upon a replacement of dirtyentry. This results in lowering the access speed. The control of thisembodiment as described above is therefore preferable.

[0073] An example of page control of the memory controller 3 accordingto this embodiment will be explained next with reference to timingcharts shown in FIGS. 7, 8, and 9, in comparison with the prior art.FIG. 7 shows the waveforms in case of a page hit. Referring to FIG. 7,after a column address strobe signal/CAS goes low to be active at thesecond cycle of a clock signal CLK, data DQ is read out from the mainmemory 4 from the fourth cycle.

[0074] After that, when the column address strobe signal/CAS and a writeenable signal/WE go low to be active at the ninth cycle of the clocksignal CLK, the data DQ is written in the main memory 4. In case of FIG.7, since the second write access to the main memory 4 is made withrespect to the same page as the first readout access, a page hit occurswithout any overhead.

[0075]FIG. 8 shows the waveforms in page control by the conventionalmemory controller. Referring to FIG. 8, a page miss occurs at the ninthcycle of a clock signal CLK, and precharging is done when a row addressstrobe signal/RAS and a write enable signal/WE go low. After that, therow address strobe signal/RAS goes low at the 11th cycle aftercompletion of precharging, and another page is activated. Furthermore,when a column address strobe signal/CAS and the write enable signal/WEgo low at the 13th cycle, data DQ is written in another page of the mainmemory 4.

[0076] In this way, when a page miss occurs, writing the data DQ iscompleted at the 16th cycle, and overhead for four cycles arises incomparison with the case of page hit in which the write access iscompleted at the 12th cycle. In this portion alone, nearly 33% overheadarises. But, all cycles are not filled with only such accesses. Whencache replacements frequently take place upon interrupt response or taskswitch, nearly 20% overhead arises.

[0077]FIG. 9 shows the waveforms in page control according to thisembodiment in which precharging is done immediately after a read accessfollowed by a store-back access. Referring to FIG. 9, after a columnaddress strobe signal/CAS goes low to be active at the second cycle of aclock signal CLK, data DQ is read out from the main memory 4 from thefourth cycle. This read access corresponds to the operation of (2) shownin FIG. 5. Before the execution of this read access, a page controlsignal CTL goes high to be active in response to a replacement of dirtyentry detected by the replacement detection/notification circuit 11.

[0078] When the row address strobe signal/RAS and write enable signal/WEgo low at the seventh cycle corresponding to the final stage of the readaccess while the page control signal CTL is at high level, prechargingis done (the precharge instruction can be issued at the final stage ofthe access in terms of SDRAM specifications). When the read operation iscompleted, the page control signal CTL goes low.

[0079] After that, the row address strobe signal/RAS goes low at theninth cycle after completion of precharging, so as to activate anotherpage. Furthermore, when the column address strobe signal/CAS and writeenable signal/WE go low at eleventh cycle, data DQ is written in anotherpage in the main memory 4. This write access corresponds to theoperation of (3) shown in FIG. 5.

[0080] According to the page control of this embodiment, sinceprecharging is done in the read operation, the write access to anotherpage in the main memory 4 is completed at the 14th cycle, and sooverhead is reduced to two cycles in comparison with the case of FIG. 8.In other words, overhead can be halved in comparison with theconventional method, and reduced to around 10% even when cachereplacements frequently occur upon interrupt response or task switch. Inthose cases, however increased the cache size is, cache misses can notbe avoided. Hence, in those cases, this embodiment is superior toincreasing the cache size in terms of improving the performance.

[0081] The second embodiment of the present invention will be describedbelow. The first embodiment mentioned above is a case of one main memory(for example, only one DRAM bank). But, in some cases, a plurality ofDRAMs may be connected. Or, like an SDRAM, a chip includes a pluralityof banks, and different pages can be simultaneously activated if theyare present on different banks. In the latter case, the DRAM can beaccessed as if there were a plurality of DRAMs in the chip.

[0082] This second embodiment is applied to a system that has aplurality of DRAMs, and can issue access requests to any of thosememories. FIG. 10 shows the arrangement of an SDRAM as an example ofmain memory 4 used in a memory control system (computer system)according to the second embodiment. The SDRAM shown in FIG. 10 comprisesa storage area 21 consisting of a plurality of banks 21 a to 21 d. Thesebanks 21 a to 21 d may be provided on different chips or a single chip.

[0083] Read/write access, active/idle switching control of each page,and the like are done on the basis of control signals supplied from acontrol signal latch circuit 22 to three terminals RAS, CAS, and WE. Thecontrol signal latch circuit 22 latches control signals generated bydecoding a chip select signal/CS, a row address strobe signal/RAS, acolumn address strobe signal/CAS, and a write enable signal/WE by acommand decoder 25.

[0084] When a page is activated or precharged to the idle state in eachof the banks 21 a to 21 d, the location on a memory cell array isdesignated based on an address externally supplied to an addressbuffer/register & bank selection circuit 26. In this case, the page isdesignated by selecting a word line in accordance with an upper rowaddress supplied from the address buffer/register & bank selectioncircuit 26 to the banks 21 a to 21 d.

[0085] When data is read out from or written in the banks 21 a to 21 d,the location on the memory cell array is also designated based on anaddress externally supplied to the address buffer/register & bankselection circuit 26. In this case, a word line is selected inaccordance with an upper row address supplied from the addressbuffer/register & bank selection circuit 26 to the banks 21 a to 21 d,and a bit line is selected in accordance with a lower column addresssupplied via a column address counter 24.

[0086] When a plurality of banks 21 a to 21 d to be selected by a chipselect signal are connected like this embodiment, an externally inputaddress generally contains not only a column address in a lower portion,and a row address in a portion upper than the column address, but also,identification information indicating a bank to be accessed, in aportion upper than the row address. The address buffer/register & bankselection circuit 26 selects a bank on the basis of the identificationinformation contained in the address.

[0087] Data DQ to be read out or written according to the addressexternally supplied to the address buffer/register & bank selectioncircuit 26 is input from or output to an external circuit via an I/Odata buffer/register 27.

[0088] Note that the SDRAM used in this embodiment has various operationmodes. The count operation of the column address counter 24 isappropriately controlled in accordance with mode control signalssupplied from the command decoder 25 and address buffer/register & bankselection circuit 26 via a mode register 23.

[0089] The aforementioned blocks operate in synchronism with a clocksignal CLK externally supplied to a clock buffer 28.

[0090] In the system in which the main memory 4 comprises a plurality ofDRAMs (banks), when a replacement of dirty entry is performed, if theread address of new data to be loaded into the cache memory 2 and thewrite address of the entry to be replaced are located on different chips(different banks in case of SDRAM), no precharge is necessary in thechip (bank) containing the destination of the earlier read access, andthe page selected at that time is preferably kept active.

[0091] More specifically, if the accessed page is precharged simply bydetecting occurrence of replacement of dirty entry in the cache memory 2like the first embodiment, when the destinations of the earlier readaccess and the succeeding write access are located on different chips(banks), unnecessarily precharging is done. This causes an decrease inaccess speed.

[0092] In order to avoid this problem, in this second embodiment,address comparison is made in the cache memory 2 with divided upper andlower addresses. The location to divide is changed in accordance withthe size of DRAM connected. In this case, the address is divided so thatthe upper address portion contains identification information indicatinga chip (bank) to access. It is thereby judged that an access having adifferent upper addresses from that corresponding to an entry to bereplaced is for a chip (bank) different from that containing the entry.

[0093] In case of detecting that the current access is to a differentchip (bank), the cache memory 2 controls the replacementdetection/notification circuit 11 not to output a page control signalinstructing the memory controller 3 to precharge the read-accessed page.With this control, unnecessarily precharging can be avoided, and fasteraccess to the main memory 4 can be attained as a whole.

[0094] Address assignment used in this embodiment will be describedbelow with reference to FIGS. 11A and 11B. For example, when the mainmemory 4 uses four 8-bit wide 64-Mbit SDRAMs connected via a 32-bit bus,a 32-bit address is divided as shown in FIG. 11A.

[0095] The 0th and 1st bits on the LSB side are used for designatingread/write in units of bytes. The 2nd to 10th bits are used as a columnaddress to be output to the SDRAM. The 11th to 22nd bits are used as arow address to be output to the SDRAM. The 23rd and 24th bits are usedas a bank address for designating a bank, which is also output to theSDRAM. Note that the 25th to 31st bits on the MSB side of the bankaddress are not used.

[0096] In case that the arrangement of the cache memory 2 is 16 Kbytes/4ways (4 Kbytes/way: each way has the arrangement shown in FIG. 2),address comparison is done with respect to the 12th to 31st bits, asshown in FIG. 11B. The address comparison is done with dividing theaddress into the 12th to 22nd bits (lower address) and the 23rd to 31stbits (upper address) in accordance with the DRAM size. Note that the 0thto 11th bits are not used in this address comparison on the cache.

[0097] After the address comparison is done as shown in FIG. 2 using theupper and lower addresses shown in FIG. 11B, when the upper and loweraddresses coincides with those of the aimed address, a cache hit occurs,and the corresponding data can be input/output only by accessing thecache memory 2.

[0098] When the addresses do not coincide, a cache miss occurs, and theoldest entry which has not been accessed for the longest time in thecache memory 2 is selected and replaced by new data. If the entry to bereplaced is not dirty (“dirty” means that the data of the entry has beenrewritten to be different from the corresponding part in the main memory4), new data is read out from the main memory 4 to update the entry ofthe cache memory 2.

[0099] When the entry to be replaced is dirty, a replacement must bedone, in which the data of the entry is written out in the main memory4, and other data is read out from the main memory 4 to update the entryof the cache memory 2. When the replacement is executed, in thisembodiment, if the upper addresses (23rd to 31st bits) of successiveaccesses coincide with each other, the successive accesses are to anidentical chip (bank), so a page control signal is output from thereplacement detection/notification circuit 11 for precharging and thecache entry is replaced, like the first embodiment.

[0100] On the other hand, even when the entry to be replaced is dirty,if the upper addresses (23rd to 31st bits) do not coincide with eachother, the successive accesses are to different chips (banks), so nopage miss occurs on the main memory 4 in those accesses. Hence, in thiscase, the cache entry is replaced without the replacementdetection/notification circuit 11 asserting any page control signalindicating that the current access is attendant upon a replacement ofdirty entry.

[0101] As described above, according to the second embodiment, even whena dirty entry is replaced, if successive accesses made for thereplacement are to different memories in the main memory 4, prechargingthe earlier accessed page is not performed. Unnecessarily prechargingcan be avoided therefore. This brings about a faster access speed to themain memory 4 as a whole even in a system comprising a plurality ofmemories.

[0102] Note that the arrangements, operations, and the like of theindividual units described in the above embodiments are only forexamples of the present invention, and the technical scope of thepresent invention must not be construed to be limited by them. Thepresent invention contains various changes and modifications of theabove embodiments without departing from the spirit and principalfeature of the invention.

[0103] For example, in the above embodiments, a signal to be output whena replacement of dirty entry is detected uses a dedicated page controlsignal. But, if a signal line indicating the type of access request hasa margin for bit assignment, a type indicating that a store-back access(write access attendant upon a replacement of dirty entry) follows thecurrent access may be added as one of the access types.

[0104] In the above embodiments, a DRAM (more specifically an SDRAM) isused as an example of the main memory 4. But, the present invention canbe applied to any other memories as long as they have a fast page mode.

[0105] In the second embodiment descried above, a control is made not toassert any page control signal when it is judged that successiveaccesses are to different banks in the main memory 4. But, the memorycontroller 4 may be informed that no page miss will occur.

[0106] The page control of each of the above embodiments is implementedby hardware such as a sequencer. But, the page control flow shown inFIG. 6 may be implemented by running a program stored in the ROM 5 orRAM 4 shown in FIG. 4, for example. Note that the ROM 5 or RAM 4 may beconnected to the CPU 1 via a bus 16 shown in FIG. 12, and the programmay be stored in them. A program that makes the computer operate toprovide the aforementioned functions may be recorded on a recordingmedium such as a CD-ROM, and the page control may be implemented withthe program installed in the computer. As the recording medium, inaddition to the ROM, RAM, and CD-ROM mentioned above, a floppy disk, ahard disk, a magnetic tape, a magnetooptical disk, a nonvolatile memorycard, and the like may be used.

[0107] When the functions of each of the above embodiments areimplemented not only by executing the supplied program to the computerbut also by executing the program in cooperation with an OS (operatingsystem) or another application software that is running on the computer,or when those functions are implemented by executing some or all of theprocesses of the supplied program by an function expansion board or unitof the computer, such program is included in the embodiments of thepresent invention.

[0108] According to the present invention, when an access made to a mainmemory is attendant upon a replacement of dirty entry in a cache device,the currently active page in the main memory is precharged to return tothe idle state when the earlier access is completed. Time waste due tooverhead upon cache replacements can be shortened thereby. Inparticular, when the present invention is applied to a computer system,time waste due to overhead can be greatly shortened even when cachereplacements frequently takes place upon interrupt response or taskswitch, and a faster access speed to the memory can be attained.

[0109] According to another feature of the present invention, whenaccess is made to the main memory attendant upon a replacement of dirtyentry in the cache device, and successive accesses attendant upon thereplacement are made to the same one of main memories, the currentlyactive page in the main memory is precharged to return to the idle statewhen the earlier access is completed. In this case, even when a dirtyentry in the cache device is replaced, if successive accesses attendantupon the replacement are made to different main memories, respectively,the currently active page is not precharged in any of the main memorieswhen the corresponding earlier access is completed. Unnecessarilyprecharging is thereby avoided, and so time waste due to overhead can beshortened.

[0110] According to still another feature of the present invention, whena signal indicating that the current access is attendant upon areplacement of dirty entry in a cache device, is supplied from the cachedevice to a memory controller, the signal can be included in a signalthat indicates the type of access to the main memory. Hence, nodedicated signal line need be assigned in addition to existing signallines, and the circuit scale can be prevented from increasing.

What is claimed is:
 1. A memory controller for controlling access to amain memory, said controller having a mode for keeping the accessed pagein said main memory active even after the access is completed, and saidcontroller comprising state control circuit for controlling to prechargethe accessed page in said main memory to return to the idle state uponcompletion of preceding access on condition that access to said mainmemory is attendant upon a replacement of dirty entry in a cache device.2. A memory controller for controlling access to a plurality of mainmemories, said controller having a mode for keeping the accessed page inone of said main memories active even after the corresponding access iscompleted, and said controller comprising state control circuit forcontrolling to precharge the accessed page in one of said main memoriesto return to the idle state upon completion of preceding access oncondition that successive accesses attendant upon a replacement of dirtyentry in a cache device are made to the same one of said main memories.3. A store-back cache device comprising: detection/notification circuitfor detecting occrrence of replacement of dirty entry, and sending asignal to a controller of a main memory to indicate whether or not thecurrent access to said main memory is attendant upon said replacement.4. A device according to claim 3, wherein said detection/notificationcircuit sends said signal in a state of being included in a signal forindicating a type of access to said main memory.
 5. A store-back cachedevice comprising: detection/notification circuit for detectingoccurrence of replacement of dirty entry in a cache and a condition thatsuccessive accesses attendant upon said replacement are made to the sameone of a plurality of main memories, to send a signal to a controller ofsaid main memories for indicating whether or not the current access tosaid one of said main memories is attendant upon said replacement.
 6. Adevice according to claim 5, wherein said detection/notification circuitdetermines whether said successive accesses are made to the same one ofsaid main memories or to different ones of said main memories bycomparing identification information assigned to each of said mainmemories, said information being allocated in each address used foraccessing.
 7. A memory control system comprising a store-back cachedevice located between a CPU and a main memory, and a memory controllerwhich is connected to said cache device to control access to said mainmemory, wherein said memory controller has a mode for keeping theaccessed page in said main memory active even after the access iscompleted, said cache device comprises detection/notification circuitfor detecting occurrence of replacement of dirty entry, and sending asignal to said memory controller to indicate whether or not the currentaccess to said main memory is attendant upon said replacement, and saidmemory controller comprises state control circuit for controlling toprecharge the accessed page in said main memory to return to the idlestate upon completion of preceding access to said main memory when saidmemory controller receives said signal from said cache device toindicate the access attendant upon said replacement.
 8. A systemaccording to claim 7, wherein said detection/notification circuit sendssaid signal in a state of being included in a signal for indicating atype of access to said main memory.
 9. A memory control systemcomprising a store-back cache device located between a CPU and aplurality of main memories, and a memory controller which is connectedto said cache device to control access to said main memories, whereinsaid memory controller has a mode for keeping the accessed page in oneof said main memories active even after the corresponding access iscompleted, said cache device comprising detection/notification circuitfor detecting occurrence of replacement of dirty entry and a conditionthat successive accesses attendant upon said replacement are made to thesame one of said main memories, to send a signal to said memorycontroller for indicating whether or not the current access to said oneof said main memories is attendant upon said replacement, and saidmemory controller comprises state control circuit for controlling toprecharge the accessed page in said one of said main memories to returnto the idle state upon completion of preceding access when said memorycontroller receives said signal from said cache device to indicate theaccess attendant upon said replacement.
 10. A memory control method forcontrolling access to a main memory in a computer system which comprisesa store-back cache device and a memory controller having a mode forkeeping the accessed page in said main memory active even after theaccess is completed, said method comprising: a first step of detectingoccurrence of replacement of dirty entry in said cache device; and asecond step of making said memory controller control to precharge theaccessed page in said main memory to return to the idle state uponcompletion of preceding access to said main memory attendant on saidreplacement when said replacement of dirty entry is detected.
 11. Amethod according to claim 10, further comprising, between said first andsecond steps, a step of making said cache device send a signal to saidmemory controller, said signal indicating whether or not the currentaccess to said main memory is attendant upon said replacement.
 12. Amemory control method for controlling access to a plurality of mainmemories in a computer system which comprises a store-back cache deviceand a memory controller having a mode for keeping the accessed page inone of said main memories active even after the corresponding access iscompleted, said method comprising the steps of: detecting occurrence ofreplacement of dirty entry in said cache device, and a condition thatsuccessive accesses attendant upon said replacement are made to the sameone of said main memories; and making said memory controller control toprecharge the accessed page in said one of said main memories to returnto the idle state upon completion of preceding access to said mainmemory attendant on said replacement when said occurrence of thereplacement and the successive accesses to the same one of said mainmemories are detected.
 13. A recording medium that records a program tooperate a computer system comprising a store-back cache device locatedbetween a CPU and a main memory, and a memory controller which isconnected to said cache device to control access to said main memory,said memory controller having a mode for keeping the accessed page insaid main memory active even after the access is completed, said programmaking said computer system function as: means for detecting occurrenceof replacement of dirty entry in said cache device, and then informingsaid memory controller; and means for making said memory controllercontrol to return the accessed page in said main memory to the idlestate upon completion of preceding access to said main memory attendanton said replacement when said memory controller is informed of adetection occurrence of said replacement of dirty entry.
 14. A recordingmedium that records a program to operate a computer system comprisingstore-back cache device located between a CPU and a plurality of mainmemories, and a memory controller which is connected to said cachedevice to control access to said main memories, said memory controllerhaving a mode for keeping the accessed page in one of said main memoriesactive even after the corresponding access is completed, said programmaking said computer system function as: means for detecting occurrenceof replacement of dirty entry in said cache device and a condition thatsuccessive accesses attendant upon said replacement are made to the sameone of said main memories, for making said cache device inform saidmemory controller; and means for making said memory controller controlto return the accessed page in said one of said main memories to theidle state upon completion of preceding access attendant on saidreplacement when said memory controller is informed by said cachedevice.